Any #Vivado users here? Is it possible that the IP Core using AXI-Stream are buggy as hell?

* AXI4-Stream Broadcaster with a N width input and two outputs seems to set the width to 2*N on either output in the GUI, no matter if I set it manually.
* Connecting to a Slice with M width input only works from first output. But it also tells me I could connect m_axis_tvalid[1:0] which is not width M...

🤯 😩

#fpga #xilinx