Guess why this UART code loops forever on Star64 #JH7110 #RISCV SBC
Article: https://lupyuen.codeberg.page/articles/privilege.html#wait-forever-in-uart-transmit
Here's the answer: UART Registers on Star64 #JH7110 are spaced differently from QEMU!
Article: https://lupyuen.codeberg.page/articles/privilege.html#uart-registers-are-spaced-differently
Let's find out why #NuttX on Star64 #JH7110 gets stuck ... When we enter a Critical Section
Article: https://lupyuen.codeberg.page/articles/privilege.html#critical-section-doesnt-return
#RISCV "mstatus" Register won't work in #NuttX RTOS because we're running in Supervisor Mode ... Let's fix it for #JH7110
Article: https://lupyuen.codeberg.page/articles/privilege.html#critical-section-doesnt-return
We change #RISCV "mstatus" to "sstatus" in Apache #NuttX RTOS ... Because it runs in Supervisor Mode on Star64 #JH7110
Article: https://lupyuen.codeberg.page/articles/privilege.html#risc-v-privilege-levels
Switching #NuttX from #RISCV Machine Mode to Supervisor Mode
Article: https://lupyuen.codeberg.page/articles/privilege.html#risc-v-machine-mode-becomes-supervisor-mode
#NuttX Kernel Mode executes NuttX Apps in unprivileged User Mode
Article: https://lupyuen.codeberg.page/articles/privilege.html#nuttx-flat-mode-becomes-kernel-mode
Check out the other #RISCV ports of Apache #NuttX RTOS
Article: https://lupyuen.codeberg.page/articles/privilege.html#other-risc-v-ports-of-nuttx
We're porting Apache #NuttX RTOS to Star64 #JH7110 SBC ... Let's talk about the #RISCV Privilege Levels and UART Registers
https://lupyuen.codeberg.page/articles/privilege