verilog joke
someone performing a poorly timed action that causes a chain of catastrophic consequences affecting the entire graph... call that "ex propagation"
I was recently thinking about this: we believe that clock domain crossing gadgets can get rid of xs, as long as the fraction of time the input is an x is small enough (because otherwise they would produce xs when actually used as clock domain boundaries). So, have people tried to do circuits with areas that are not sync in any normal way to a clock, but still preserve the "is rarely x" property on their outputs (though not necessarily internal signals)?
(It does seem to offer at very most few benefits, but what I'm after is a succinct argument for why that's e.g. always majorized by some more conventional circuit.)
