#KiCad people: how can I set up my board & net class constraints so I will get a DRC error if vias of different nets are <0.5mm apart, but vias of the same net only error if <0.254mm apart? I can't figure it out and wading through DRC errors because I have same-net vias less than 0.5mm apart is tedious and may make me miss an actual error. Attached is a screenshot of the pertinent part of JLCPCB's capabilities page as well as KiCad's board constraints page.