Ok, people who understand Amigas - if I have a CPU that doesn't consume a bus cycle to read the next instruction, I should be able to write to a register on every even cycle, right? Copper is going to have to read from RAM but can then do a write on the next odd cycle? So if I dedicate the CPU and Copper to this, I should be able to update custom chip registers on 75% of the available cycles in hblank when nothing else is trying to grab them?