Wow nextpnr's ECP5 PLL calculator is just wizardry.
"Please make me a 25.175MHz clock from this 25MHz input clock"
"Easy: first, divide that input by 8 for a 3.125MHz reference. Feed that into the VCO with a 145x feedback multiplier, for a 453.125MHz frequency reference. Finally, stick an 18x divider on the VCO, and there you go: 25.1736MHz, 55ppm off from what you wanted."
🤯
The especially clever thing it does here, is the middle bit. It wants to get a high VCO frequency so that it can divide back down and hit close to the mark, while also inheriting the lower jitter from that high VCO clock.
Normally what you do is mess with the output divider and the feedback divider, to get an output clock that's a multiple of your reference input. In effect you get to divide your input once, and multiply it once.
But the calculator here uses a little trick to get a 2nd divide!
The PLL block's signal path goes: input clock -> divider -> VCO with 4 outputs -> divider on each output -> out. The feedback path for the VCO can hook into any of the 4 outputs, post-their divider, and has an extra divider of its own.
The output divider plus the feedback divider are the one multiplication from the previous post.
But! Each output on the PLL block also has an enable bit, that controls whether the signal is actually output to the rest of the FPGA.
So what ecppll does is: it does the divide-then-multiply thing on the first output line, but then disables that output. That clock signal never goes out to the FPGA. Its only job is to provide a path that lets it multiply the VCO frequency up to whatever is convenient, so that it can then divide it by some other completely different value on output number 2, and hit the target frequency you requested. So it can divide-then-multiply-then-divide to hit your requested output.
And sure, in doing that, you lose one of your 4 PLL outputs. But then again, you're composing some bizarre fancy frequency, and those other outputs have to be divisions of that. You're probably going to be okay without them.
Plus the ECP5 in has 4 PLL blocks, so you still have another 3 to play with for generating any other frequencies you need!
Oh and also when doing this wacky loop-de-loop through the PLL block, that second lane that actually gets output also gets phase-shifted, by an absolutely minuscule amount. I... have no idea why it's doing that. Looking at the generated Verilog, I think it's trying to null out the phase difference between the input and output? In this case I don't think it helps too much since the clocks aren't multiples of each other, but if they were that would mean the clock edges would be in sync.
@danderson Do you think they do that to reduce noise in the supply mesh, or for EMC reasons?
