Hey, #Electronics folks!
Has anyone seen such an output for a ramp coming out of a DAC?
This is produced by a simple counter counting from 0 to 4095 and then wrapping.
The sharp dips are absolutely stable and deterministic. They occur at bit switches but I don't seem to get my head around why.
Identical curves on two different DAC peripherals on the same μC and even across different chips/boards (I'm almost certain it's a software problem).

So, first of all, thanks for the input, @Pat, @cstanhope, @Segebodo, @timjan, @alinanorakari !

It turns out it was sort of digital but mostly clock related. For some reason, the GCLK Generator 1 was set to 120 MHz (div 1) while in other examples it was set to a lower value of 12 MHz, i.e. higher div (10 for example). Well: now the sawtooth is smooth as a baby’s butt.
The thing is: I only found this by going through a dozen graphical representations of the configurations - which were buggy. Not sure why it was GCLK1, by the way. The datasheet says GCLK_DAC must be lower than 12 MHz casually under 47.6.3 Operating conditions ^^ (I set it to 20 MHz (div 6) and it still worked though).

So, at least my hunch was right: This was indeed not a nonmonotonous DAC (because, wow, that would’ve been awful!).
My second hunch was right too: There’s way more experience to gather.

Lessons learned:

1. Always make sure your clock settings are okay.
2. Get used to looking for crucial info on speed and timing under sub-paragraph 6.3+ 😵
3. If you can, chose a product with a clean, functional and stable IDE+toolchain (or use your own).