But 0x4400 0000 is NOT documented in Reference Manual! 😲 Now we know a secret ... BL602 talks to LMAC Firmware at Address 0x4400 0000 🤫

github.com/bouffalolab/bl_docs

Moving away from LMAC Firmware (since we got no code) ... Let's study the mysterious Library "libwifi" ... Which has been decompiled into C by BraveHeartFLOSSDev

github.com/BraveHeartFLOSSDev/

"wifi_main" lives in the mysterious Library "libwifi" ... Let's study the decompiled C code (thanks to BraveHeartFLOSSDev and Ghidra)

github.com/lupyuen/bl602nutcra

"wifi_main" calls "ke_evt_schedule" to do Tasks ... GitHub Search shows that "ke_evt_schedule" is also defined in ... AliOS! 😲

github.com/lupyuen/bl602nutcra

But does "ke_evt_schedule" really come from AliOS? Not quite ... "ke_evt_schedule" actually comes from ... CEVA RivieraWaves! 😲

github.com/mclown/AliOS-Things

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@PawelK @lupyuen The code in my repos? It's Reverse Engineered code. It's still not complete but I'm much closer now. I have 6 files that I need to get RE'd to C.

@PawelK @lupyuen I guess it is my child in some ways. Mr. Lee has been working on it too. The code is RV32IMFC on a processor that supports Rv32imafcb. He's building better firmware for it and perhaps my work will be helpful.

@lupyuen That's so much cleaner than the first version uploaded. It was also using a custom ported Processor that is also in the repository but not yet available in Ghidra. I'm just glad that you are finding it useful. Libwifi should contain 112 object files but 6 were excluded because of errors, I'll get them up when I can get them decompiled.

@PawelK @lupyuen Ghidra loads them but won't disassemble. It's an error regarding memory and my custom processor has reduced the number of errors. This is a memory issue that I need to address soon. Ghidra is a beast and 9.2.2 had the same quality code as IDA Pro on Arm. Gamiee and I had a little competition comparing the output of the two. He had to admit that it was powerful but it doesn't produce pretty code. Verbose Chainsaw is the actual test that was done. The capabilities are greatly improved in 10.0.0.

@AmpBenzScientist
Out of mem err or out of bounds write or read mem err?

I could be willing to get Your and Gaimees disassembler test harmess to contribute to llvm if it would be ok with You Two.

@lupyuen

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@AmpBenzScientist
Btw Benzinski some guys around llvm and clang wanna invest some effort into making their disassembler perfect. One of its targets is riscv.

@lupyuen

@AmpBenzScientist @lupyuen

If You wanted to play with llvms disassemblers, i could link you to guys from project etc. They got perfect code quality and architecture for c++ its written in.

@PawelK @lupyuen After reading deep into SLED and SLEIGH so I could port a processor, I see why Ghidra is so effective. Given the troublesome nature of RISC-V disassembly, I would recommend SLEIGH because of the flexibility of it. Even with Ghidra, I spent 3 months working on this. It took about a week to get the first results and I've been doing work on Ghidra since then.

I might have to pass as I want to get involved more with Ghidra and Rizin development.

@AmpBenzScientist
Mkay. I wished ghidra and llvm got more synchronized. Llvms speed and low mem reqs kick ass. But we could try to use archspecs (isnt it whats sleight used for?) in sleigh and friends into llvm.

@lupyuen

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@AmpBenzScientist
Oh my, i just learned sleigh was introed partly or contributed to by one and only cristina cifuentes.

Oh my. I still have her dissertation somewhere. I was intoxicating myself in early childhood with reading it.

@lupyuen

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