Lup Yuen Lee 李立源 @lupyuen@qoto.org

Barebones TCC #RISCV Compiler in #WebAssembly 🎉

Source: https://lupyuen.github.io/tcc-riscv32-wasm/

#Ox64 BL808 UART Controller has Leaky Reads and Writes ... But there's a simple fix!

Article: https://lupyuen.codeberg.page/articles/plic3.html#leaky-reads-in-uart

TCC #RISCV Compiler, compiled to #WebAssembly by #ZigLang Compiler ... Generates correct ELF Code! 🎉

Source: https://github.com/lupyuen/tcc-riscv32-wasm#tcc-webassembly-runs-ok-in-a-web-browser

Running TCC #RISCV Compiler inside the Web Browser ... Thanks to #ZigLang Compiler 👍

Source: https://github.com/lupyuen/tcc-riscv32-wasm#test-the-tcc-webassembly-in-a-web-browser

Strange problems in #Ox64 BL808 UART and Interrupt Controller ... Let's investigate the alligator in the vest

Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-and-plic-troubles

TCC: The simple C Compiler for #RISCV ... Can we compile TCC to #WebAssembly with #ZigLang Compiler? 🤔

Source: https://github.com/lupyuen/tcc-riscv32-wasm

"expect" script works OK for testing our #Ox64 BL808 Emulator 🎉

Source: https://github.com/lupyuen/nuttx-tinyemu

Here's how we handle a UART Interrupt on #Ox64 BL808 #RISCV SBC

Article: https://lupyuen.codeberg.page/articles/plic3.html#uart-interrupt

Try our Online Demo of Apache #NuttX Real-Time Operating System ... Powered by TinyEMU #RISCV Emulator 👍

Source: https://nuttx.apache.org/demo/

Weak Ordering in the #Ox64 BL808 Memory Management Unit (#RISCV T-Head C906) ... Causes problems with the UART and Interrupt Controllers! Here's how we fix it

Article: https://lupyuen.codeberg.page/articles/plic3

Fixed the MMU Cache for #Ox64 BL808 #RISCV SBC on Apache #NuttX RTOS 👍

Source: https://github.com/apache/nuttx/pull/11585

Remember to Flush the MMU Cache when switching Page Tables ... On #RISCV T-Head C906 and #Ox64 BL808 SBC

Article: https://lupyuen.codeberg.page/articles/mmu.html#appendix-flush-the-mmu-cache-for-t-head-c906

We copied the #NuttX UART Driver from PineCone BL602 to #Ox64 BL808 ... And it works! 👍

Article: https://lupyuen.codeberg.page/articles/plic2.html#appendix-uart-driver-for-ox64

Flushing the MMU Cache for #RISCV T-Head C906 .... Tested OK with #Ox64 BL808 and Apache #NuttX RTOS 👍

Source: https://gist.github.com/lupyuen/def8fb96245643c046e5f3ad6c4e3ed0#found-solution-flush-the-cache-with-dcachecall-dcacheiall-icacheiall

Remember to enable MMU Strong Ordering on #Ox64 BL808 and #RISCV T-Head C906 ... Or strange things will happen 😬

Article: https://lupyuen.codeberg.page/articles/plic2.html#trouble-with-interrupt-priority

Emulator for #Ox64 BL808 #RISCV SBC @PINE64 ... Boots OK with Apache #NuttX RTOS! 🎉

Article: https://lupyuen.codeberg.page/articles/tinyemu2.html

Dispatching and Completing the UART Interrupts ... On #Ox64 BL808 #RISCV SBC with Apache #NuttX RTOS

Article: https://lupyuen.codeberg.page/articles/plic2.html#dispatch-the-interrupt

Apache #NuttX RTOS in Kernel Mode ... Works great with TinyEMU #RISCV Emulator! 🎉

Source: https://github.com/lupyuen/ox64-tinyemu/tree/smode#start-nuttx-kernel-in-supervisor-mode

How we handle a #RISCV Interrupt with Platform-Level Interrupt Controller (PLIC)

Article: https://lupyuen.codeberg.page/articles/plic2.html#handle-the-interrupt

How #Ox64 BL808 #RISCV SBC boots Apache #NuttX RTOS ... Exactly like Linux

Source: https://lupyuen.codeberg.page/articles/app