Lup Yuen Lee 李立源 @lupyuen@qoto.org

Let's boot Apache #NuttX RTOS over the Network with U-Boot and TFTP

Source: https://github.com/lupyuen/nuttx-star64#boot-from-network-with-u-boot-and-tftp

We test the #RISCV Armbian and Yocto #Linux Images ... On #Star64 JH7110 SBC

Article: https://lupyuen.codeberg.page/articles/star64.html#linux-images-for-star64

Let's inspect the #Linux Images for Star64 JH7110 #RISCV SBC @PINE64 ... And figure out how to boot Apache #NuttX RTOS!

Article: https://lupyuen.codeberg.page/articles/star64

Booting Apache #NuttX RTOS (and Linux) over the Network with TFTP

Source: https://github.com/lupyuen/nuttx-star64#boot-from-network-with-u-boot-and-tftp

Okinawa Black Sugar Sourdough

Recipe: https://lupyuen.codeberg.page/articles/sourdough.html#okinawa-black-sugar-sourdough

Fixing our #NuttX Boot Code ... So that it runs in #RISCV Supervisor Mode on #Star64 JH7110 SBC

Source: https://github.com/lupyuen/nuttx-star64#fix-the-nuttx-boot-code

Up Next: Apache #NuttX RTOS on Star64 JH7110 #RISCV SBC!

Article: https://lupyuen.codeberg.page/articles/riscv.html?5#jump-to-start

Switching #RISCV from Machine Mode to Supervisor Mode ... Just change the "m" registers to "s"

Source: https://github.com/lupyuen/nuttx-star64#downgrade-nuttx-to-supervisor-mode

Here's the complete list of #RISCV Instructions

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#other-instructions

Quick tour of #RISCV Instructions

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#other-instructions

Here's how #Linux gets the #RISCV Hart ID from OpenSBI

Source: https://github.com/lupyuen/nuttx-star64#downgrade-nuttx-to-supervisor-mode

Adapting 32-bit Assembly Code for 64-bit … Easy peasy for #RISCV!

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#32-bit-vs-64-bit-risc-v

Loading the Vector Table in #RISCV Assembly

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#load-interrupt-vector

Apache #NuttX RTOS runs in #RISCV Supervisor Mode on #Star64 JH7110 SBC

Source: https://github.com/lupyuen/nuttx-star64#risc-v-privilege-levels

How we Disable Interrupts in #RISCV Assembly ... And a curious way to loop forever

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#disable-interrupts

Here's how we fetch the CPU ID in #RISCV Assembly

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#get-cpu-id

Apache #NuttX RTOS fails to get the #RISCV Hart ID (CPU ID) ... Let's find out why

Source: https://github.com/lupyuen/nuttx-star64#nuttx-fails-to-get-hart-id

Let's walk through the #RISCV Boot Code in Apache #NuttX RTOS

Article: https://lupyuen.codeberg.page/articles/riscv.html?4#risc-v-boot-code-in-nuttx

What happens when Apache #NuttX RTOS boots on #RISCV QEMU Emulator? Let's check the RISC-V Disassembly

Article: https://lupyuen.codeberg.page/articles/riscv.html?3#qemu-starts-nuttx

Apache #NuttX RTOS runs in #RISCV Supervisor Mode on #Star64 JH7110 SBC

Source: https://github.com/lupyuen/nuttx-star64#risc-v-privilege-levels