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Jedes der wenigen Male, wenn ich die Hügelstraße entlang laufe, frage ich mich, wer das bei halbwegs klarem Verstand für erstrebenswert halten konnte. Und das zeigt noch gar nicht die der Straße zugewandte Seite des Staatstheaters 😵 Die Stadt hat hier einfach eine Narbe.
@SheDrivesMobility

Es windet, kühlt ab, zieht zu und sieht aus als würde es bald regnen: Ich liebe alles daran! 🌧️⛈️🌧️

Schön zu sehen, wenn ein Verkehrsversuch so zuende geht.

Versteht sich von selbst, dass das viel zu wenig viel zu langsam ist, um eine herbeizuführen.

Running Xilinx ISE 14.7 in Docker

In an earlier post, I wanted to get Xilinx ISE 14.7 to run on an up-to-date Ubuntu 22.04 LTS which failed miserably.

So, instead I chose the container route using Docker. This seems to work quite well, so I'd like to share it with anyone interested.

I've packed a working setup in a Gitlab repository.

ISE 14

bowfinger.de/blog/2022/07/runn

Does Anyone Actually Cycle in Switzerland!?

I'm always being told that people won't cycle where it's hilly, and Switzerland is a pretty hilly country, so does anybody actually cycle there? Well, yes. I...

youtu.be/pWnreLG_cvc

Okay, wir benennen jetzt einfach "Elektrizität" in "E-Fuel" um und die hält endlich den Rand! ?

Kleinanzeigen-Edition 😉

Servierwagen und Einlegefächer, Tür und Schubladen für Ikea Kallax durch gefahren. Mit nem Leihesel von @sigosharing

Pah, Biblis ist ein weiteres L gewachsen. Und da sage nochmal einer, Atomkraft sei harmlos! 😄

So, first of all, thanks for the input, @Pat, @cstanhope, @Segebodo, @timjan, @alinanorakari !

It turns out it was sort of digital but mostly clock related. For some reason, the GCLK Generator 1 was set to 120 MHz (div 1) while in other examples it was set to a lower value of 12 MHz, i.e. higher div (10 for example). Well: now the sawtooth is smooth as a baby's butt.
The thing is: I only found this by going through a dozen graphical representations of the configurations - which were buggy. Not sure why it was GCLK1, by the way. The datasheet says GCLK_DAC must be lower than 12 MHz casually under 47.6.3 Operating conditions ^^ (I set it to 20 MHz (div 6) and it still worked though).

So, at least my hunch was right: This was indeed not a nonmonotonous DAC (because, wow, that would've been awful!).
My second hunch was right too: There's way more experience to gather.

**Lessons learned:**
1. Always make sure your clock settings are okay.
1. Get used to looking for crucial info on speed and timing under sub-paragraph 6.3+ 😵
1. If you can, chose a product with a clean, functional and stable IDE+toolchain (or use your own).

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Hey, folks!
Has anyone seen such an output for a ramp coming out of a DAC?
This is produced by a simple counter counting from 0 to 4095 and then wrapping.
The sharp dips are absolutely stable and deterministic. They occur at bit switches but I don't seem to get my head around why.
Identical curves on two different DAC peripherals on the same μC and even across different chips/boards (I'm almost certain it's a software problem).

Oh, schön, gerade implodiert unsere (9 Kündigungen bei vllt. 12-14 Stellen). sein in Auto-Bratwurstland ist soooo schön!

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